RISC-V

Develop a new RISC-V Core

  • pre 1 year ago

    What would be the starting point for developing a new RISC-V Core?

    Anonymous
    pre 1 year ago

    The first step is to select required instruction set that suits for your requirements. The RISC-V specifications contains the list of instructions and their details. The specification is in the following link https://riscv.org/specifications/. The list of instructions can be found in the pages starting from 115.

    You have to choose one of the the instruction set defined under headings Base Integer Instruction Set (Headings 2, 3, 4 and 5). Other extensions can be added based on the requirement. e.g:- for a floating point calculations, include “F”-extension.

    pre 1 year ago

    @gajalakshan thank you for the clarification. I believe @kasun has already explained the requirement to you. We are planing on implementing a beginner friendly RISC-V processor. I believe using RV32I Base Integer instruction set would be a good idea. May be we can start working on arithmetic instruction set as a start. Do you have any suggestions for the architecture to be used in a RISC-V processor?

    pre 1 year ago

    For the architecture you can simply refer to this lecture series (https://www.youtube.com/watch?v=CDO28Esqmcg&list=PLhwVAYxlh5dvB1MkZrcRZy6x_a2yORNAu) based on MIPS ISA which is a similar to RISC V ( lecture 23 onward) he explains a simple MIPS processor implementation. (We are also focusing on developing a riscv processor targeted for IoT purposes for that we also going to develop a very simple single cycle executed processor for learning purposes in verilog.)

    pre 1 year ago

    @vithurson thanks for the reference. May be we can draft an architecture and collaboratively develop a processor.

    pre 1 year ago

    I have already watched around 30 videos of the lecture series which vithurson mentioned and now I’m following the RISC-V specification for an initial implementation. 🙂

    pre 1 year ago

    Hi All,

    I have initiated a repository at https://github.com/chiphackers/AtomRV32

    For now, I have come up with the following folder structure:
    |rtl
    |—-|modules
    |—-|—-|alu
    |—-|—-|instruction_decoder
    |—-|—-|register_file
    |tests

    We can start the module wise implementation. Please let me know the github usernames if you like to start contributing.

    pre 1 year ago

    Hi All,

    Please review the draft architecture inspired by lowRISC architecture. Suggest the edits needed. (You can edit the original document itself if you like to add something. )

    https://chiphackers.com/docs/atomrv32/

     

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