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@savinduherath

Active 4 years ago
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    udara edited the doc Terms of use 2 years ago

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    udara created the doc Terms of use 2 years ago

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    udara edited the doc Privacy Policy 2 years ago

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    udara created the doc Privacy Policy 2 years ago

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    udara posted an update 2 years ago

    Restarting development of ChipHackers after a year

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    udara posted an update in the group Group logo of HackathonsHackathons 3 years ago

    RTL playground is a beta version of the RTL hackathon. Try it out !!!

    ChipHackers
    https://hackathons.chiphackers.com/rtl-playground
    ChipHackers

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    udara edited the doc Learning Portal Development Project 4 years ago

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    udara created the doc Learning Portal Development Project 4 years ago

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    udara created the group Group logo of HackathonsHackathons 4 years ago

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    udara edited the doc Introduction to Checkers 4 years ago

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    udara created the doc Introduction to Checkers 4 years ago

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    udara posted an update in the group Group logo of RISC-VRISC-V 4 years ago

    Need to update the spec for

    » AtomRV32 Design Specifications
    https://chiphackers.com/docs/atomrv32/
    Introduction AtomRV32 is a CPU based on RISC-V instruction set architecture. The motivation behind AtomRV32 is designing a very simple CPU that is easy to learn and adopt. Status This project is in pre-Alpha…

    [Read more]

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    udara created the group Group logo of RISC-VRISC-V 4 years ago

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    udara started the topic Cache for RISC V in the forum RISC-V 4 years ago

    What should be the specifications for first level cache which can be used with RISC-V processor

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    udara replied to the topic Develop a new RISC-V Core in the forum RISC-V 4 years ago

    Hi All,

    Please review the draft architecture inspired by lowRISC architecture. Suggest the edits needed. (You can edit the original document itself if you like to add something. )

    https://chiphackers.com/docs/atomrv32/

     

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