savinduherath

udara edited the doc Terms of use 2 years ago
udara created the doc Terms of use 2 years ago
udara edited the doc Privacy Policy 2 years ago
udara created the doc Privacy Policy 2 years ago
udara posted an update 3 years ago

Restarting development of ChipHackers after a year
udara posted an update in the group Hackathons 3 years ago

RTL playground is a beta version of the RTL hackathon. Try it out !!!

ChipHackers

https://hackathons.chiphackers.com/rtl-playground

ChipHackers
udara and rameshfdo are now friends 5 years ago
udara and savinduherath are now friends 5 years ago
udara edited the doc Learning Portal Development Project 5 years ago
udara created the doc Learning Portal Development Project 5 years ago
udara created the group Hackathons 5 years ago
udara edited the doc Introduction to Checkers 5 years ago
udara created the doc Introduction to Checkers 5 years ago
udara and viduneth are now friends 5 years ago
udara posted an update in the group RISC-V 5 years ago

Need to update the spec for

» AtomRV32 Design Specifications

https://chiphackers.com/docs/atomrv32/

Introduction AtomRV32 is a CPU based on RISC-V instruction set architecture. The motivation behind AtomRV32 is designing a very simple CPU that is easy to learn and adopt. Status This project is in pre-Alpha…

[Read more]
udara and sasindu are now friends 5 years ago
udara created the group RISC-V 5 years ago
udara started the topic Cache for RISC V in the forum RISC-V 5 years ago

What should be the specifications for first level cache which can be used with RISC-V processor
udara and vithurson are now friends 5 years ago
udara replied to the topic Develop a new RISC-V Core in the forum RISC-V 5 years ago

Hi All,

Please review the draft architecture inspired by lowRISC architecture. Suggest the edits needed. (You can edit the original document itself if you like to add something. )

https://chiphackers.com/docs/atomrv32/
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@savinduherath