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@savinduherath

Active 4 years ago
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    udara changed their profile picture 5 years ago

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    udara replied to the topic Develop a new RISC-V Core in the forum RISC-V 5 years ago

    Hi All,

    I have initiated a repository at https://github.com/chiphackers/AtomRV32

    For now, I have come up with the following folder structure:
    |rtl
    |—-|modules
    |—-|—-|alu
    |—-|—-|instruction_decoder
    |—-|—-|register_file
    |tests

    We can start the module wise implementation. Please let me know the github usernames if you like to start…[Read more]

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    udara changed their profile picture 5 years ago

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    udara replied to the topic Develop a new RISC-V Core in the forum RISC-V 5 years ago

    @vithurson thanks for the reference. May be we can draft an architecture and collaboratively develop a processor.

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    udara replied to the topic Develop a new RISC-V Core in the forum RISC-V 5 years ago

    @gajalakshan thank you for the clarification. I believe @kasun has already explained the requirement to you. We are planing on implementing a beginner friendly RISC-V processor. I believe using RV32I Base Integer instruction set would be a good idea. May be we can start working on arithmetic instruction set as a start. Do you have any suggestions…[Read more]

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    udara started the topic Develop a new RISC-V Core in the forum RISC-V 5 years ago

    What would be the starting point for developing a new RISC-V Core?

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    udara posted an update 5 years ago

    Building social network of ChipHackers

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