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@udara

active 1 month ago
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    udara and Profile picture of rameshfdorameshfdo are now friends 7 months ago

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    udara edited the doc Learning Portal Development Project 8 months ago

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    udara created the doc Learning Portal Development Project 8 months ago

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    udara created the group Group logo of HackathonsHackathons 8 months ago

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    udara edited the doc Introduction to Checkers 8 months ago

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    udara created the doc Introduction to Checkers 8 months ago

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    udara posted an update in the group Group logo of RISC-VRISC-V 9 months ago

    Need to update the spec for

    » AtomRV32 Design Specifications
    https://chiphackers.com/docs/atomrv32/
    Introduction AtomRV32 is a CPU based on RISC-V instruction set architecture. The motivation behind AtomRV32 is designing a very simple CPU that is easy to learn and adopt. Status This project is in pre-Alpha…

    [Read more]

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    udara created the group Group logo of RISC-VRISC-V 9 months ago

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    udara started the topic Cache for RISC V in the forum RISC-V 9 months ago

    What should be the specifications for first level cache which can be used with RISC-V processor

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    udara replied to the topic Develop a new RISC-V Core in the forum RISC-V 9 months ago

    Hi All,

    Please review the draft architecture inspired by lowRISC architecture. Suggest the edits needed. (You can edit the original document itself if you like to add something. )

    https://chiphackers.com/docs/atomrv32/

     

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    udara replied to the topic Develop a new RISC-V Core in the forum RISC-V 9 months ago

    Hi All,

    I have initiated a repository at https://github.com/chiphackers/AtomRV32

    For now, I have come up with the following folder structure:
    |rtl
    |—-|modules
    |—-|—-|alu
    |—-|—-|instruction_decoder
    |—-|—-|register_file
    |tests

    We can start the module wise implementation. Please let me know the github usernames if you like to start…[Read more]

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