udara

udara started the topic Cache for RISC V in the forum RISC-V 5 years ago

What should be the specifications for first level cache which can be used with RISC-V processor
udara and vithurson are now friends 5 years ago
udara replied to the topic Develop a new RISC-V Core in the forum RISC-V 5 years ago

Hi All,

Please review the draft architecture inspired by lowRISC architecture. Suggest the edits needed. (You can edit the original document itself if you like to add something. )

https://chiphackers.com/docs/atomrv32/
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udara replied to the topic Develop a new RISC-V Core in the forum RISC-V 5 years ago

Hi All,

I have initiated a repository at https://github.com/chiphackers/AtomRV32

For now, I have come up with the following folder structure:
|rtl
|—-|modules
|—-|—-|alu
|—-|—-|instruction_decoder
|—-|—-|register_file
|tests

We can start the module wise implementation. Please let me know the github usernames if you like to start…[Read more]
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ashanuka and udara are now friends 5 years ago
udara replied to the topic Develop a new RISC-V Core in the forum RISC-V 5 years ago

@vithurson thanks for the reference. May be we can draft an architecture and collaboratively develop a processor.
udara replied to the topic Develop a new RISC-V Core in the forum RISC-V 5 years ago

@gajalakshan thank you for the clarification. I believe @kasun has already explained the requirement to you. We are planing on implementing a beginner friendly RISC-V processor. I believe using RV32I Base Integer instruction set would be a good idea. May be we can start working on arithmetic instruction set as a start. Do you have any suggestions…[Read more]
udara started the topic Develop a new RISC-V Core in the forum RISC-V 5 years ago

What would be the starting point for developing a new RISC-V Core?
udara posted an update 5 years ago

Building social network of ChipHackers

@udara