Co-simulating Verilog Design in Python (Using MyHDL)
MyHDL is a hardware description language (HDL) written in Python. It is also used as a hardware verification language (HVL)
Designs written in MyHDL can be converted to Verilog or VHDL. Also it allows simulating design using built-in simulator or
other RTL simulators like ModelSim, VCS and Iverilog. MyHDL can be installed using pip
pip install myhdl
ModelSim is a popular RTL simulator (Popular among Windows users). ModelSim can be downloaded and installed from here. After the installation add C:\intelFPGA_pro\20.4\modelsim_ase\win32aloem to the PATH environment variable.
In order to use ModelSim for co-simulation a little bit more work is needed. MyHDL co-simulation uses the PLI interface of the simulators. To use this feature we need to compile a shared library distributed with MyHDL. Compiling a library means we need a C compiler but luckily ModelSim is shipped with its own MinGW compiler toolset. We will use it to build the library here.
cd "WORK_DIR" git clone https://github.com/myhdl/myhdl.git cd myhdl\cosimulation\modelsim-win # Below command compiles the library. Please use your ModelSim installation path if it's different from the default C:\intelFPGA_pro\20.4\modelsim_ase\gcc-4.2.1-mingw32vc12\bin\gcc -g -IC:\\intelFPGA_pro\\20.4\\modelsim_ase\\include -o myhdl_vpi.dll .\myhdl_vpi.c -LC:\\intelFPGA_pro\\20.4\\modelsim_ase\\win32aloem -lmtipli -shared cd test python .\test_all.py