Co-simulating Verilog Design in Python (Using MyHDL)   Setup MyHDL MyHDL is a hardware description language (HDL) written in Python. It is also used as a hardware verification language (HVL) Designs written in MyHDL can be converted to Verilog or VHDL. Also it allows simulating design using built-in simulator or other RTL simulators like ModelSim, […]

Mathematics of Deep Learning   1 Introduction Deep learning(DL) is becoming increasingly popular within machine learning community for wide range of applications like speech recognition [1], computer vision [2] and natural language processing [3]. The major advantage in DL is its ability to learn from raw input data. Traditional machine learning techniques require experts in […]

UART (Universal Asynchronous Receiver Transmitter)   UART is a widely used asynchronous communication protocol. It is the most common protocol to transmit data from PC to microcontroller/FPGA boards. UART is the successor of RS-232 and RS-458 asynchronous protocols. RS-232 was very popular in early age of computers where it is used for computer serial port. The […]

SPI (Serial Peripheral Interface)   SPI is serial communication protocol used by microcontrollers and sensors. It is widely used to due to its simplicity and ability to operate at high data rates. However there are several disadvantages like, only single master is supported, slaves can not communicate to each other, number of wires used increases […]

SystemVerilog from the beginning The tutorial mainly focus on the SystemVerilog constructs and how could we use the language for both the “Design” and “Verification”. The concepts will be built from the scratch and are mainly discussed using sample designs. In the introduction we will give a quick introduction on the language basics and the […]

What is Code Coverage ? Code Coverage is an estimation of how much percentage of your RTL design is really tested in your testbench. Ideally, a well tested RTL design should have 100% code coverage. There are different types of code coverage metrics : Line coverage This metric shows the percentage of RTL lines that […]

Datapath pipelining The concept of pipelining extracted from the concept of production lines of vehicles, makes use of breaking down a task into several subtasks and using parallel processing to complete those subtasks. There are two main objectives achieved using pipelining in a digital electronic system. Increasing the throughput of the system. Running the system […]

I2C (Inter Integrated Circuit Communication) I2C – Inter-Integrated Circuit Communication is a widely used protocol for communication between modules of a digital systems both inside a chip as well as on a circuit board. Operating on two frequencies 100 MHz and 400 MHz, I2C is categorized as a slow mode of communication but widely useful […]

HDMI High Definition Multimedia Interface is a widely used interface for communicating audio visual data among electronic devices. This interface introduced in 2002 by a group of 7 electronic product manufacturing companies, facilitates the communication of uncompressed video and both compressed and uncompressed audio from a HDMI source device to another complaint device such as […]

Ripple Carry Adder Basic gates such as NOT, OR, AND, NAND and NOR are used to carry out basic arithmetic operations like addition, subtraction, multiplication and division in processors. Addition is the most basic arithmetic operation, as subtraction (a series of negative addition), multiplication (a series of positive addition) and division (a series of negative […]

Verilog Gate Level Modeling Gate Level Modeling describes a hardware circuit using the logic gates and their interconnections. Verilog has become popular because it supports behavioral modeling where the user doesn’t have to worry about which logic gates needs to be used. In contrast, Gate level modeling requires you to take decisions on which gates […]

Verilog Testbench Writing – A step by step guide Testbenches are modules written to test a design or a part of a design by giving it different inputs and observing the output using a simulator. The testbench intends to facilitate the simulation tools by giving the required input in required order and taking the output […]

Verilog Generator Blocks Verilog generate blocks are the method of avoiding unnecessary code repetition for the codes having same architecture. Description It must be defined within a module. The port connections are realized using a special variable referred as genvar. genvar is an integer variable which should be kept in a positive value. The value is valid only […]

Blocking and Non-blocking Statements In Hardware description languages, blocking and non-blocking statements are used to generate either sequential or combinational logic. As the name suggests, a blocking statement blocks the next statement in the queue from executing until the current statement has finished execution. Contradictory to this, a non-blocking statement can execute in parallel with […]

Synopsys design constraints (SDC) is a format used to provide additional infromation required by EDA tools for Synthesis and Place & Route. It is based on standard Tcl language therefore any valid Tcl command can be used in .sdc file. In addition to Tcl commands there are several SDC specific commands which are used to […]