
What is Code Coverage ?
Code Coverage is an estimation of how much percentage of your RTL design is really tested in your testbench. Ideally, a well tested RTL design should have 100% code coverage. There are different types of code coverage metrics :
-
Line coverage
-
Block coverage
- Conditional coverage
- Branch coverage
- Toggle coverage
- FSM coverage
This metric shows the percentage of RTL lines that are executed.
Reports RTL blocks that our executed
This tutorial will explain how to use covered with iverilog to generate coverage reports. As the example design we will be using a simple test bench.
Setting Up: Installing iverilog & covered:
[cce lang=”bash”]
sudo apt-get install iverilog
sudo apt-get install covered
[/cce]
Step 1: Writing the testbench
[cce lang=”verilog”]
module line_coverage;
reg a = 0;
reg b = 0;
initial begin
$display(“starting simulation”);
if( a == 1) begin
$display(“didn’t come here”);
b = 1;
end else begin
$display(“came here”);
b = 0;
end
end
endmodule
[/cce]
Step 3: Running covered and iverilog
[cce lang=”bash”]
covered score -t line_coverage -v line_coverage.v -o db.cdd -vpi
iverilog line_coverage.v covered_vpi.v -m covered.vpi
vvp -M
covered report -d v cov.cdd
[/cce]
Step 4: Covered Report
[cce]
::::::::::::::::::::::::::::::::::::::::::::::::::
:: ::
:: Covered — Verilog Coverage Verbose Report ::
:: ::
::::::::::::::::::::::::::::::::::::::::::::::::::
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ GENERAL INFORMATION ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* Report generated from CDD file : cov.cdd
* Reported by : Module
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ LINE COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Module/Task/Function Filename Hit/ Miss/Total Percent hit
———————————————————————————————————————
$root NA 0/ 0/ 0 100%
line_coverage line_coverage.v 2/ 1/ 3 67%
———————————————————————————————————————
Accumulated 2/ 1/ 3 67%
———————————————————————————————————————
Module: line_coverage, File: line_coverage.v
————————————————————————————————————-
Missed Lines
8: b = 1
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ TOGGLE COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Toggle 0 -> 1 Toggle 1 -> 0
Module/Task/Function Filename Hit/ Miss/Total Percent hit Hit/ Miss/Total Percent hit
———————————————————————————————————————
$root NA 0/ 0/ 0 100% 0/ 0/ 0 100%
line_coverage line_coverage.v 0/ 2/ 2 0% 0/ 2/ 2 0%
———————————————————————————————————————
Accumulated 0/ 2/ 2 0% 0/ 2/ 2 0%
———————————————————————————————————————
Module: line_coverage, File: line_coverage.v
————————————————————————————————————-
Signals not getting 100% toggle coverage
Signal Toggle
———————————————————————————————————
a 0->1: 1’h0
……………………. 1->0: 1’h0 …
b 0->1: 1’h0
……………………. 1->0: 1’h0 …
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ COMBINATIONAL LOGIC COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Logic Combinations
Module/Task/Function Filename Hit/Miss/Total Percent hit
———————————————————————————————————————
$root NA 0/ 0/ 0 100%
line_coverage line_coverage.v 1/ 1/ 2 50%
———————————————————————————————————————
Accumulated 1/ 1/ 2 50%
———————————————————————————————————————
Module: line_coverage, File: line_coverage.v
————————————————————————————————————-
Missed Combinations (* = missed value)
=========================================================================================================
Line # Expression
=========================================================================================================
6: if( a == 1 )
|–1—|
Expression 1 (1/2)
^^^^^^^^^^^^^ – ==
E | E
=0=|=1=
*
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ FINITE STATE MACHINE COVERAGE RESULTS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
State Arc
Module/Task/Function Filename Hit/Miss/Total Percent Hit Hit/Miss/Total Percent hit
———————————————————————————————————————
$root NA 0/ 0/ 0 100% 0/ 0/ 0 100%
line_coverage line_coverage.v 0/ 0/ 0 100% 0/ 0/ 0 100%
———————————————————————————————————————
Accumulated 0/ 0/ 0 100% 0/ 0/ 0 100%
[/cce]
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