What is Code Coverage ?

Code Coverage is an estimation of how much percentage of your RTL design is really tested in your testbench. Ideally, a well tested RTL design should have 100% code coverage. There are different types of code coverage metrics :

Line coverage

This metric shows the percentage of RTL lines that are executed.

Block coverage

Reports RTL blocks that our executed

Conditional coverage
Branch coverage
Toggle coverage
FSM coverage

This tutorial will explain how to use covered with iverilog to generate coverage reports. As the example design we will be using a simple test bench.

Setting Up: Installing iverilog & covered:

1
2
3

sudo apt-get install iverilog

sudo apt-get install covered

Step 1: Writing the testbench

1
2
3
4
5
6
7
8
9
10
11
12
13
14

module line_coverage;
reg a = 0;
reg b = 0;
initial begin
$display("starting simulation");
if( a == 1) begin
$display("didn't come here");
b = 1;
end else begin
$display("came here");
b = 0;
end
end
endmodule

Step 3: Running covered and iverilog

1
2
3
4
5
6
7

covered score -t line_coverage -v line_coverage.v -o db.cdd -vpi

iverilog line_coverage.v covered_vpi.v -m covered.vpi

vvp -M <root>/lib/ivl a.out

covered report -d v cov.cdd

Step 4: Covered Report

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
::::::::::::::::::::::::::::::::::::::::::::::::::
:: ::
:: Covered -- Verilog Coverage Verbose Report ::
:: ::
::::::::::::::::::::::::::::::::::::::::::::::::::

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
GENERAL INFORMATION
~
* Report generated from CDD file : cov.cdd

* Reported by : Module

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~ LINE COVERAGE RESULTS ~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Module/Task/Function Filename Hit/ Miss/Total Percent hit
---------------------------------------------------------------------------------------------------------------------
$root NA 0/ 0/ 0 100%
line_coverage line_coverage.v 2/ 1/ 3 67%
---------------------------------------------------------------------------------------------------------------------
Accumulated 2/ 1/ 3 67%
---------------------------------------------------------------------------------------------------------------------

Module: line_coverage, File: line_coverage.v
-------------------------------------------------------------------------------------------------------------
Missed Lines

8: b = 1

~
TOGGLE COVERAGE RESULTS
~
Toggle 0 -> 1 Toggle 1 -> 0
Module/Task/Function Filename Hit/ Miss/Total Percent hit Hit/ Miss/Total Percent hit
---------------------------------------------------------------------------------------------------------------------
$root NA 0/ 0/ 0 100% 0/ 0/ 0 100%
line_coverage line_coverage.v 0/ 2/ 2 0% 0/ 2/ 2 0%
---------------------------------------------------------------------------------------------------------------------
Accumulated 0/ 2/ 2 0% 0/ 2/ 2 0%
---------------------------------------------------------------------------------------------------------------------

Module: line_coverage, File: line_coverage.v
-------------------------------------------------------------------------------------------------------------
Signals not getting 100% toggle coverage

Signal Toggle
---------------------------------------------------------------------------------------------------------
a 0->1: 1'h0
......................... 1->0: 1'h0 ...
b 0->1: 1'h0
......................... 1->0: 1'h0 ...

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
COMBINATIONAL LOGIC COVERAGE RESULTS ~
~
Logic Combinations
Module/Task/Function Filename Hit/Miss/Total Percent hit
---------------------------------------------------------------------------------------------------------------------
$root NA 0/ 0/ 0 100%
line_coverage line_coverage.v 1/ 1/ 2 50%
---------------------------------------------------------------------------------------------------------------------
Accumulated 1/ 1/ 2 50%
---------------------------------------------------------------------------------------------------------------------

Module: line_coverage, File: line_coverage.v
-------------------------------------------------------------------------------------------------------------
Missed Combinations (* = missed value)

=========================================================================================================
Line # Expression
=========================================================================================================
6: if( a == 1 )
|--1---|

Expression 1 (1/2)
^^^^^^^^^^^^^ - ==
E | E
=0=|=1=
*

~~~~~
~ FINITE STATE MACHINE COVERAGE RESULTS ~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
State Arc
Module/Task/Function Filename Hit/Miss/Total Percent Hit Hit/Miss/Total Percent hit
---------------------------------------------------------------------------------------------------------------------
$root NA 0/ 0/ 0 100% 0/ 0/ 0 100%
line_coverage line_coverage.v 0/ 0/ 0 100% 0/ 0/ 0 100%
---------------------------------------------------------------------------------------------------------------------
Accumulated 0/ 0/ 0 100% 0/ 0/ 0 100%

What is Code Coverage ?

Line coverage

Block coverage

Setting Up: Installing iverilog & covered:

Step 1: Writing the testbench

Step 3: Running covered and iverilog

Leave a Reply Cancel reply