Synopsys design constraints (SDC) is a format used to provide additional infromation required by EDA tools for Synthesis and Place & Route. It is based on standard Tcl language therefore any valid Tcl command can be used in .sdc file.
In addition to Tcl commands there are several SDC specific commands which are used to provide timing, power and area informations to EDA Tools.

Below is a simple design written in Verilog. Let’s write a basic SDC file for this design.

File : test.v
module test(in, clk, out);

input in,clk;
output reg out

reg r0;

always @ (posedge clk) begin
r0 <= in;
out <= r0;


Basic SDC file example

File : test.sdc
create_clock -name clock1 -period 10 [get_ports clk]
set_input_delay 2 [get_ports in]

Line 1 : create_clock -name clock1 -period 10 [get_ports clk]

After test design is synthesized it needs to be placed and routed. In place and route (P&R), one important step is clock tree synthesize (CTR).
This step is important since clock needs to reach every sequential element at the same time (Practically this is not possible. There will be always a difference between the time a clock reach two elements.
This is known as skew. However minimizing skew is mandatory. If not the behaviour of the system would be undeterminstic).

In the verilog description, clk wire is as same as any other wire in the design(in,out). But due to above reason special care should be taken when routing clk wire.
This is done by declaring that port as a clock port using create_clock constraints.

| Parameter | Description |
| -name <clock_name> | <clock name> is equivalent to a variable name in a programming language. Other constraints will refer this clock using this name |
| -period <value> | <value> is the time taken for one period of the clock. Equivalent to inverse of the frequency |

Line 2 : set_input_delay

This is another important timing constraints. Almost all the inputs that connects to sequential elements are required to have an input_delay.
Input delay is the time taken to data be ready at the input after clock edge. This is needed since all the inputs are comming from external and there will a delay in connecting wires and IO pads.
Input delay should not exceed the clock period. Because if the input delay is higher than the clock period there is no way the receiving sequential element to sample the input.

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