Verilog Generator Blocks
Verilog generate blocks are the method of avoiding unnecessary code repetition for the codes having same architecture.
It must be defined within a module. The port connections are realized using a special variable referred as genvar. genvar is an integer variable which should be kept in a positive value. The value is valid only up to the elaboration. In the simulation it is not visible. They may only be used within a generate block. Genvar variables must be declared within the module where the genvar is used.
module not_gate(in, out); // NOT gate
assign out = ~in;
// Generator for NOT gates arranged in parallel.
reg [7:0] i;
wire [7:0] o;
for (index = 0; index < 8; index = index + 1) begin
not_gate NG( .in(i[index]), .out(o[index]));