Verilog Generator Blocks

Verilog generate blocks are the method of avoiding unnecessary code repetition for the codes having same architecture.

Description

It must be defined within a module. The port connections are realized using a special variable referred as genvar. genvar is an integer variable which should be kept in a positive value. The value is valid only up to the elaboration. In the simulation it is not visible. They may only be used within a generate block. Genvar variables must be declared within the module where the genvar is used.

Example

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module not_gate(in, out); // NOT gate 

    input in; 

    output out; 



    assign out = ~in; 

endmodule 



// Generator for NOT gates arranged in parallel. 

module test; 

    reg [7:0] i; 

    wire [7:0] o; 



    genvar index; 

    generate 

        for (index = 0; index < 8; index = index + 1) begin 

            not_gate NG( .in(i[index]), .out(o[index])); 

        end 

    endgenerate 

endmodule